View LPC2132_195834.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC
Rev. 01 -- 18 November 2004 Preliminary data sheet
1. General description
The LPC2131/2132/2138 microcontrollers are based on a 32/16 bit ARM7TDMI-STM CPU with real-time emulation and embedded trace support, that combines the microcontroller with 32 kB, 64 kB and 512 kB of embedded high speed Flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb(R) Mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM options of 8/16/32 kB, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit 8 channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.
2. Features
2.1 Key features
s 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8/16/32 kB of on-chip static RAM and 64/512 kB of on-chip Flash program memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation. s In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software. Single Flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms. s EmbeddedICE(R) RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitorTM software and high speed tracing of instruction execution. s One (LPC2131/2132) or two (LPC2138) 8 channel 10-bit A/D converters provides a total of up to 16 analog inputs, with conversion times as low as 2.44 s per channel. s Single 10-bit D/A converter provides variable analog output. (LPC2132/2138 only) s Two 32-bit timers/counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog. s Real-time clock equipped with independent power and clock supply permitting extremely low power consumption in power-save modes. s Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPITM and SSP with buffering and variable data length capabilities. s Vectored interrupt controller with configurable priorities and vector addresses.
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
s Up to 47 5 V tolerant general purpose I/O pins in tiny LQFP64 package. s Up to nine edge or level sensitive external interrupt pins available. s 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s. s On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz. s Power saving modes include Idle and Power-down. s Individual enable/disable of peripheral functions as well as peripheral clock scaling down for additional power optimization. s Processor wake-up from Power-down mode via external interrupt. s Single power supply chip with POR and BOD circuits: x CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1: Ordering information Package Name LPC2131FBD64 LPC2132FBD64 LPC2138FBD64 LQFP64 LQFP64 LQFP64 Description plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Version SOT314-2 SOT314-2 SOT314-2 Type number
3.1 Ordering options
Table 2: Ordering options Flash memory 32 kB 64 kB 512 kB RAM 8 kB 16 kB 32 kB CAN Temperature range (C) -40 to +85 -40 to +85 -40 to +85 Type number LPC2131FBD64 LPC2132FBD64 LPC2138FBD64
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
2 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
4. Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1) XTAL2 RST XTAL1
LPC2132/2138
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
PLL system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
AHB BRIDGE ARM7 local bus
AMBA AHB (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER
AHB DECODER AHB TO VPB BRIDGE VPB DIVIDER
8/16/32 kB SRAM
32/64/512 kB FLASH
VPB (VLSI peripheral bus) EINT3:0 EXTERNAL INTERRUPTS I2C SERIAL INTERFACES 0 AND 1 SCL0,1 SDA0,1 SCK0,1 CAPTURE/ COMPARE TIMER 0/TIMER 1 SPI AND SSP SERIAL INTERFACES MOSI0,1 MISO0,1 SSEL0,1 TXD0,1 UART0/UART1 RXD0,1
8 x CAP0 8 x MAT
AD0.7:0 AD1.7:0(1)
A/D CONVERTERS 0 AND 1(1)
AOUT(2)
D/A CONVERTER(2)
REAL TIME CLOCK
DSR1(1),CTS1(1), RTS1(1), DTR1(1) DCD1(1),RI1(1) RTXC1 RTXC2
VBAT
P0.31:0 P1.31:16, 1:0
GENERAL PURPOSE I/O
WATCHDOG TIMER
PWM6:1
PWM0
SYSTEM CONTROL
002aab067
(1) LPC2138 only. (2) LPC2132/2138 only.
Fig 1. Block diagram.
9397 750 14008 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
3 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
5. Pinning information
5.1 Pinning
54 P0.19/MAT1.2/MOSI1/CAP1.2 53 P0.18/CAP1.3/MISO1/MAT1.3 55 P0.20/MAT1.3/SSEL1/EINT3
52 P1.30/TMS
64 P1.27/TDO
56 P1.29/TCK
60 P1.28/TDI
57 RESET
62 XTAL1
61 XTAL2
58 P0.23
59 VSSA
63 VREF
P0.21/PWM5/AD1.6(1)/CAP1.3 P0.22/AD1.7(1)/CAP0.0/MAT0.0 RTXC1 P1.19/TRACEPKT3 RTXC2 VSS VDDA P1.18/TRACEPKT2 P0.25/AD0.4/AOUT(2)
1 2 3 4 5 6 7 8 9
49 VBAT 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/RI1(1)/EINT2/AD1.5(1) 44 P1.21/PIPESTAT0 43 VDD 42 VSS 41 P0.14/DCD1(1)/EINT1/SDA1 40 P1.22/PIPESTAT1 39 P0.13/DTR1(1)/MAT1.1/AD1.4(1) 38 P0.12/DSR1(1)/MAT1.0/AD1.3(1) 37 P0.11/CTS1(1)/CAP1.1/SCL1 36 P1.23/PIPESTAT2 35 P0.10/RTS1(1)/CAP1.0/AD1.2(1) 34 P0.9/RXD1/PWM6/EINT3 33 P0.8/TXD1/PWM4/AD1.1(1) P1.24/TRACECLK 32
002aab068
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
51 VDD P0.6/MOSI0/CAP0.2/AD1.0(1) 30
LPC2131/2132/2138
P0.26/AD0.5 10 P0.27/AD0.0/CAP0.1/MAT0.1 11 P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0.2 13 P0.29/AD0.2/CAP0.3/MAT0.3 14 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16
P0.31 17
VSS 18
P0.0/TXD0/PWM1 19
P1.31/TRST 20
P0.1/RXD0/PWM3/EINT0 21
P0.2/SCL0/CAP0.0 22
VDD 23
P1.26/RTCK 24
VSS 25
P0.3/SDA0/MAT0.0/EINT1 26
P0.4/SCK0/CAP0.1/AD0.6 27
P1.25/EXTIN0 28
P0.5/MISO0/MAT0.1/AD0.7 29
(1) LPC2138 only. (2) LPC2132/2138 only.
Fig 2. Pinning.
9397 750 14008
Preliminary data sheet
Rev. 01 -- 18 November 2004
P0.7/SSEL0/PWM2/EINT2 31
50 VSS
4 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
5.2 Pin description
Table 3: Symbol P0.0 to P0.31 Pin description Pin Type I/O Description Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bi-directional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pin P0.24 is not available. P0.0/TXD0/ PWM1 P0.1/RXD0/ PWM3/EINT0 19 21 O O I O I P0.2/SCL0/ CAP0.0 P0.3/SDA0/ MAT0.0/EINT1 22 26 I/O I I/O O I P0.4/SCK0/ CAP0.1/AD0.6 27 I/O I I P0.5/MISO0/ MAT0.1/AD0.7 29 I/O O I P0.6/MOSI0/ CAP0.2/AD1.0 30 I/O I I P0.7/SSEL0/ PWM2/EINT2 31 I O I P0.8/TXD1/ PWM4/AD1.1 33 O O I P0.9/RXD1/ PWM6/EINT3 34 I O I TXD0 -- Transmitter output for UART0. PWM1 -- Pulse Width Modulator output 1. RXD0 -- Receiver input for UART0. PWM3 -- Pulse Width Modulator output 3. EINT0 -- External interrupt 0 input SCL0 -- I2C0 clock input/output. Open drain output (for I2C-bus compliance). CAP0.0 -- Capture input for Timer 0, channel 0. SDA0 -- I2C0 data input/output. Open drain output (for I2C-bus compliance). MAT0.0 -- Match output for Timer 0, channel 0. EINT1 -- External interrupt 1 input. SCK0 -- Serial clock for SPI0. SPI clock output from master or input to slave. CAP0.1 -- Capture input for Timer 0, channel 0. AD0.6 -- A/D converter 0, input 6. This analog input is always connected to its pin. MISO0 -- Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave. MAT0.1 -- Match output for Timer 0, channel 1. AD0.7 -- A/D converter 0, input 7. This analog input is always connected to its pin. MOSI0 -- Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. CAP0.2 -- Capture input for Timer 0, channel 2. AD1.0 -- A/D converter 1, input 0. This analog input is always connected to its pin. Available in LPC2138 only. SSEL0 -- Slave Select for SPI0. Selects the SPI interface as a slave. PWM2 -- Pulse Width Modulator output 2. EINT2 -- External interrupt 2 input. TXD1 -- Transmitter output for UART1. PWM4 -- Pulse Width Modulator output 4. AD1.1 -- A/D converter 1, input 1. This analog input is always connected to its pin. Available in LPC2138 only. RXD1 -- Receiver input for UART1. PWM6 -- Pulse Width Modulator output 6. EINT3 -- External interrupt 3 input.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
5 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table 3: Symbol
Pin description ...continued Pin 35 Type O I I Description RTS1 -- Request to Send output for UART1. Available in LPC2138 only. CAP1.0 -- Capture input for Timer 1, channel 0. AD1.2 -- A/D converter 1, input 2. This analog input is always connected to its pin. Available in LPC2138 only. CTS1 -- Clear to Send input for UART1. Available in LPC2138 only. CAP1.1 -- Capture input for Timer 1, channel 1. SCL1 -- I2C1 clock input/output. Open drain output (for I2C-bus compliance) DSR1 -- Data Set Ready input for UART1. Available in LPC2138 only. MAT1.0 -- Match output for Timer 1, channel 0. AD1.3 -- A/D converter input 3. This analog input is always connected to its pin. Available in LPC2138 only. DTR1 -- Data Terminal Ready output for UART1. Available in LPC2138 only. MAT1.1 -- Match output for Timer 1, channel 1. AD1.4 -- A/D converter input 4. This analog input is always connected to its pin. Available in LPC2138 only. DCD1 -- Data Carrier Detect input for UART1. Available in LPC2138 only. EINT1 -- External interrupt 1 input. SDA1 -- I2C1 data input/output. Open drain output (for I2C-bus compliance) RI1 -- Ring Indicator input for UART1. Available in LPC2138 only. EINT2 -- External interrupt 2 input. AD1.5 -- A/D converter 1, input 5. This analog input is always connected to its pin. Available in LPC2138 only. EINT0 -- External interrupt 0 input. MAT0.2 -- Match output for Timer 0, channel 2. CAP0.2 -- Capture input for Timer 0, channel 2. CAP1.2 -- Capture input for Timer 1, channel 2. SCK1 -- Serial Clock for SSP. Clock output from master or input to slave. MAT1.2 -- Match output for Timer 1, channel 2. CAP1.3 -- Capture input for Timer 1, channel 3. MISO1 -- Master In Slave Out for SSP. Data input to SPI master or data output from SSP slave. MAT1.3 -- Match output for Timer 1, channel 3. MAT1.2 -- Match output for Timer 1, channel 2. MOSI1 -- Master Out Slave In for SSP. Data output from SSP master or data input to SSP slave. CAP1.2 -- Capture input for Timer 1, channel 2. MAT1.3 -- Match output for Timer 1, channel 3. SSEL1 -- Slave Select for SSP. Selects the SSP interface as a slave. EINT3 -- External interrupt 3 input. PWM5 -- Pulse Width Modulator output 5. AD1.6 -- A/D converter 1, input 6. This analog input is always connected to its pin. Available in LPC2138 only. CAP1.3 -- Capture input for Timer 1, channel 3.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P0.10/RTS1/ CAP1.0/AD1.2
P0.11/CTS1/ CAP1.1/SCL1
37
I I I/O
P0.12/DSR1/ MAT1.0/AD1.3
38
I O I
P0.13/DTR1/ MAT1.1/AD1.4
39
O O I
P0.14/DCD1/ EINT1/SDA1
41
I I I/O
P0.15/RI1/ EINT2/AD1.5
45
I I I
P0.16/EINT0/ 46 MAT0.2/CAP0.2
I O I I I/O O
P0.17/CAP1.2/ SCK1/MAT1.2
47
P0.18/CAP1.3/ MISO1/MAT1.3
53
I I/O O
P0.19/MAT1.2/ MOSI1/CAP1.2
54
O I/O I
P0.20/MAT1.3/ SSEL1/EINT3
55
O I I
P0.21/PWM5/ AD1.6/CAP1.3
1
O I I
9397 750 14008
Preliminary data sheet
Rev. 01 -- 18 November 2004
6 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table 3: Symbol
Pin description ...continued Pin Type I I O Description AD1.7 -- A/D converter 1, input 7. This analog input is always connected to its pin. Available in LPC2138 only. CAP0.0 -- Capture input for Timer 0, channel 0. MAT0.0 -- Match output for Timer 0, channel 0. General purpose digital input/output pin. AD0.4 -- A/D converter 0, input 4. This analog input is always connected to its pin. AOUT -- D/A converter output. Available in LPC2132 and LPC2138 only. AD0.5 -- A/D converter 0, input 5. This analog input is always connected to its pin. AD0.0 -- A/D converter 0, input 0. This analog input is always connected to its pin. CAP0.1 -- Capture input for Timer 0, channel 1. MAT0.1 -- Match output for Timer 0, channel 1. AD0.1 -- A/D converter 0, input 1. This analog input is always connected to its pin. CAP0.2 -- Capture input for Timer 0, channel 2. MAT0.2 -- Match output for Timer 0, channel 2. AD0.2 -- A/D converter 0, input 2. This analog input is always connected to its pin. CAP0.3 -- Capture input for Timer 0, Channel 3. MAT0.3 -- Match output for Timer 0, channel 3. AD0.3 -- A/D converter 0, input 3. This analog input is always connected to its pin. EINT3 -- External interrupt 3 input. CAP0.0 -- Capture input for Timer 0, channel 0. General purpose digital output only pin. Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 0 through 15 of port 1 are not available. TRACEPKT0 -- Trace Packet, bit 0. Standard I/O port with internal pull-up. TRACEPKT1 -- Trace Packet, bit 1. Standard I/O port with internal pull-up. TRACEPKT2 -- Trace Packet, bit 2. Standard I/O port with internal pull-up. TRACEPKT3 -- Trace Packet, bit 3. Standard I/O port with internal pull-up. TRACESYNC -- Trace Synchronization. Standard I/O port with internal pull-up. LOW on TRACESYNC while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset. PIPESTAT0 -- Pipeline Status, bit 0. Standard I/O port with internal pull-up. PIPESTAT1 -- Pipeline Status, bit 1. Standard I/O port with internal pull-up.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P0.22/AD1.7/ 2 CAP0.0/MAT0.0
P0.23 P0.25/AD0.4/ AOUT P0.26/AD0.5
58 9
I/O I O
10
I I I O
P0.27/AD0.0/ 11 CAP0.1/MAT0.1
P0.28/AD0.1/ 13 CAP0.2/MAT0.2
I I O
P0.29/AD0.2/ 14 CAP0.3/MAT0.3
I I O
P0.30/AD0.3/ EINT3/CAP0.0
15
I I I
P0.31 P1.0 to P1.31
17
O I/O
P1.16/ TRACEPKT0 P1.17/ TRACEPKT1 P1.18/ TRACEPKT2 P1.19/ TRACEPKT3 P1.20/ TRACESYNC P1.21/ PIPESTAT0 P1.22/ PIPESTAT1
9397 750 14008
16 12 8 4 48
O O O O O
44 40
O O
Preliminary data sheet
Rev. 01 -- 18 November 2004
7 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table 3: Symbol
Pin description ...continued Pin 36 32 28 24 Type O O I I/O Description PIPESTAT2 -- Pipeline Status, bit 2. Standard I/O port with internal pull-up. TRACECLK -- Trace Clock. Standard I/O port with internal pull-up. EXTIN0 -- External Trigger Input. Standard I/O with internal pull-up. RTCK -- Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional pin with internal pull-up. LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate as Debug port after reset. TDO -- Test Data out for JTAG interface. TDI -- Test Data in for JTAG interface. TCK -- Test Clock for JTAG interface. TMS -- Test Mode Select for JTAG interface. TRST -- Test Reset for JTAG interface. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Input to the RTC oscillator circuit. Output from the RTC oscillator circuit. Ground: 0 V reference. Analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. 3.3 V power supply: This is the power supply voltage for the core and I/O ports. Analog 3.3 V power supply: This should be nominally the same voltage as VDD but should be isolated to minimize noise and error. This voltage is used to power the on-chip PLL. A/D converter reference: This should be nominally the same voltage as VDD but should be isolated to minimize noise and error. Level on this pin is used as a reference for A/D convertor. RTC power supply: 3.3 V on this pin supplies the power to the RTC.
P1.23/ PIPESTAT2 P1.24/ TRACECLK P1.25/EXTIN0 P1.26/RTCK
P1.27/TDO P1.28/TDI P1.29/TCK P1.30/TMS P1.31/TRST RESET
64 60 56 52 20 57
O I I I I I
XTAL1 XTAL2 RTXC1 RTXC2 VSS VSSA VDD VDDA
62 61 3 5
I O I O
6, 18, 25, 42, I 50 59 23, 43, 51 7 I I I
VREF
63
I
VBAT
49
I
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
8 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM(R) architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
* The standard 32-bit ARM set. * A 16-bit Thumb set.
The Thumb set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-Chip Flash program memory
The LPC2131/2132/2138 incorporate a 32 kB, 64 kB and 512 kB Flash memory system respectively. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When the LPC2131/2132/2138 on-chip bootloader is used, 32/64/500 kB of Flash memory is available for user code. The LPC2131/2132/2138 Flash memory provides minimum of 10,000 erase/write cycles and 10 years of data-retention.
6.3 On-Chip static RAM
On-Chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2131/2132/2138 provide 8/16/32 kB of static RAM.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
9 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.4 Memory map
The LPC2131/2132/2138 memory maps incorporate several distinct regions, as shown in the following figures. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either Flash memory (the default) or on-chip static RAM. This is described in Section 6.21 "System control".
4.0 GB AHB PERIPHERALS 3.75 GB VPB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xE000 0000
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB
0x8000 0000 BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF TOTAL OF 64 kB ON-CHIP STATIC RAM (LPC2138) TOTAL OF 16 kB ON-CHIP STATIC RAM (LPC2132) TOTAL OF 8 kB ON-CHIP STATIC RAM (LPC2131) 0x4000 4000 0x4000 3FFF 0x4000 2000 0x4000 1FFF 0x4000 0000 0x0008 0000 0x0007 FFFF 0x0001 0000 0x0000 FFFF 0x0000 8000 0x0000 7FFF 0x0000 0000
1.0 GB
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2138) TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2132) TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2131)
0.0 GB
002aab069
Fig 3. LPC2131/2132/2138 memory map.
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
10 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Table 4: Block WDT ARM Core ARM Core TIMER0 TIMER1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only Embedded ICE, DbgCommRX Embedded ICE, DbgCommTX Match 0 to 3 (MR0, MR1, MR2, MR3) Capture 0 to 3 (CR0, CR1, CR2, CR3) Match 0 to 3 (MR0, MR1, MR2, MR3) Capture 0 to 3 (CR0, CR1, CR2, CR3) RX Line Status (RLS) Transmit Holding Register empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) UART1 RX Line Status (RLS) Transmit Holding Register empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) (Available in LPC2138 only) PWM0 I2C0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) Capture 0 to 3 (CR0, CR1, CR2, CR3) SI (state change) 9 8 7 6 5 VIC channel # 0 1 2 3 4
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
11 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Interrupt sources ...continued Flag(s) SPIF, MODF TX FIFO at least half empty (TXRIS) RX FIFO at least half full (RXRIS) Receive Timeout (RTRIS) Receive Overrun (RORRIS) VIC channel # 10 11
Table 4: Block SPI0 SSP
PLL RTC System Control
PLL Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2) External Interrupt 3 (EINT3)
12 13 14 15 16 17 18 19 20 21
AD0 I2C1 BOD AD1
A/D Converter 0 SI (state change) Brown Out Detect A/D Converter 1 (Available in LPC2138 only)
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module contains three registers as shown in Table 5.
Table 5: Address 0xE002C000 0xE002C004 0xE002C014 Pin control module registers Name PINSEL0 PINSEL1 PINSEL2 Description Pin function select register 0 Pin function select register 1 Pin function select register 2 Access Read/Write Read/Write Read/Write
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
12 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)
The PINSEL0 register controls the functions of the pins as per the settings listed in Table 6. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Settings other than those shown in Table 6 are reserved, and should not be used.
Table 6: PINSEL0 1:0 Pin function select register 0 (PINSEL0 - 0xE002C000) Pin name P0.0 Value 0 0 1 1 3:2 P0.1 0 0 1 1 5:4 P0.2 0 0 1 1 7:6 P0.3 0 0 1 1 9:8 P0.4 0 0 1 1 11:10 P0.5 0 0 1 1 13:12 P0.6 0 0 1 1 15:14 P0.7 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.0 TXD (UART0) PWM1 Reserved GPIO Port 0.1 RXD (UART0) PWM3 EINT0 GPIO Port 0.2 SCL0 (I2C0) Capture 0.0 (Timer 0) Reserved GPIO Port 0.3 SDA0 EINT1 GPIO Port 0.4 SCK0 (SPI0) Capture 0.1 (Timer 0) AD0.6 GPIO Port 0.5 MISO0 (SPI0) Match 0.1 (Timer 0) AD0.7 GPIO Port 0.6 MOSI0 (SPI0) Capture 0.2 (Timer 0) Reserved (LPC2131/32) AD1.0 (LPC2138) GPIO Port 0.7 SSEL0 (SPI0) PWM2 EINT2 0 0 0 0 (I2C0) Match 0.0 (Timer 0) 0 0 0 Value after reset 0
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
13 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Pin function select register 0 (PINSEL0 - 0xE002C000) ...continued Pin name P0.8 Value 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.8 TXD UART1 PWM4 Reserved (LPC2131/32) AD1.1 (LPC2138) GPIO Port 0.9 RXD (UART1) PWM6 EINT3 GPIO Port 0.10 Reserved (LPC2131/32) RTS (UART1) (LPC2138) Capture 1.0 (Timer 1) Reserved (LPC2131/32) AD1.2 (LPC2138) GPIO Port 0.11 Reserved (LPC2131/32) CTS (UART1) (LPC2138) Capture 1.1 (Timer 1) SCL1 (I2C1) GPIO Port 0.12 Reserved (LPC2131/32) DSR (UART1) (LPC2138) Match 1.0 (Timer 1) Reserved (LPC2131/32) AD1.3 (LPC2138) GPIO Port 0.13 Reserved (LPC2131/32) DTR (UART1) (LPC2138) Match 1.1 (Timer 1) Reserved (LPC2131/32) AD1.4 (LPC2138) GPIO Port 0.14 Reserved (LPC2131/32) DCD (UART1) (LPC2138) EINT1 SDA1 (I2C1) GPIO Port 0.15 Reserved (LPC2131/32) RI (UART1) (LPC2138) EINT2 Reserved (LPC2131/32) AD1.5 (LPC2138) 0 0 0 0 0 0 0 Value after reset 0
Table 6: PINSEL0 17:16
19:18
P0.9
0 0 1 1
21:20
P0.10
0 0 1 1
23:22
P0.11
0 0 1 1
25:24
P0.12
0 0 1 1
27:26
P0.13
0 0 1 1
29:28
P0.14
0 0 1 1
31:30
P0.15
0 0 1 1
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
14 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.8 Pin function select register 1 (PINSEL1 - 0xE002C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in Table 7. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Settings other than those shown in the table are reserved, and should not be used.
Table 7: PINSEL1 1:0 Pin function select register 1 (PINSEL1 - 0xE002C004) Pin Name P0.16 Value 0 0 1 1 3:2 P0.17 0 0 1 1 5:4 P0.18 0 0 1 1 7:6 P0.19 0 0 1 1 9:8 P0.20 0 0 1 1 11:10 P0.21 0 0 1 1 13:12 P0.22 0 0 1 1 15:14 P0.23 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.16 EINT0 Match 0.2 (Timer 0) Capture 0.2 (Timer 0) GPIO Port 0.17 Capture 1.2 (Timer 1) SCK (SSP) Match 1.2 (Timer 1) GPIO Port 0.18 Capture 1.3 (Timer 1) MISO (SSP) Match 1.3 (Timer 1) GPIO Port 0.19 Match 1.2 (Timer 1) MOSI (SSP) Capture 1.2 (Timer 1) GPIO Port 0.20 Match 1.3 (Timer 1) SSEL (SSP) EINT3 GPIO Port 0.21 PWM5 Reserved (LPC2131/32) AD1.6 (LPC2138) Capture 1.3 (Timer 1) GPIO Port 0.22 Reserved (LPC2131/32) AD1.7 (LPC2138) Capture 0.0 (Timer 0) Match 0.0 (Timer 0) GPIO Port 0.23 Reserved Reserved Reserved 0 0 0 0 0 0 0 Value after reset 0
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
15 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Pin function select register 1 (PINSEL1 - 0xE002C004) ...continued Pin Name P0.24 Value 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Reserved Reserved Reserved Reserved GPIO Port 0.25 AD0.4 Reserved (LPC2131) AOUT (DAC) (LPC2132/38) Reserved GPIO Port 0.26 AD0.5 Reserved Reserved GPIO Port 0.27 AD0.0 Capture 0.1 (Timer 0) Match 0.1 (Timer 0) GPIO Port 0.28 AD0.1 Capture 0.2 (Timer 0) Match 0.2 (Timer 0) GPIO Port 0.29 AD0.2 Capture 0.3 (Timer 0) Match 0.3 (Timer 0) GPIO Port 0.30 AD0.3 EINT3 Capture 0.0 (Timer 0) GPIO Port Reserved Reserved Reserved 0 0 0 0 0 0 0 Value after reset 0
Table 7: PINSEL1 17:16
19:18
P0.25
0 0 1 1
21:20
P0.26
0 0 1 1
23:22
P0.27
0 0 1 1
25:24
P0.28
0 0 1 1
27:26
P0.29
0 0 1 1
29:28
P0.30
0 0 1 1
31:30
P0.31
0 0 1 1
6.9 Pin function select register 2 (PINSEL2 - 0xE002C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in Table 8. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Settings other than those shown in the table are reserved, and should not be used.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
16 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Pin function select register 2 (PINSEL2 - 0xE002C014) Description Reserved When 0, pins P1.31:26 are GPIO pins. When 1, P1.31:26 are used as Debug port. Reset value 0
Table 8: 1:0 2 3 31:30
PINSEL2 bits
When 0, pins P1.25:16 are used as GPIO pins. When 1, 0 P1.25:16 are used as Trace port. Reserved -
6.10 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.
6.10.1 Features
* Direction control of individual bits. * Separate control of output set and clear. * All I/O default to inputs after reset. 6.11 10-bit A/D converter
The LPC2131/32 contain one and the LPC2138 contains two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters with eight multiplexed channels.
6.11.1 Features
* * * * *
Measurement range of 0 V to 3.3 V. Each converter capable of performing more than 400,000 10-bit samples per second. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal. Global Start command for both converters (LPC2138 only).
6.12 10-bit D/A converter
This peripheral is available in the LPC2138 only. The D/A converter enables the LPC2138 to generate variable analog output.
6.12.1 Features
* * * *
10 bit digital to analog converter. Buffered output. Power-down mode available. Selectable speed versus power.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
17 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.13 UARTs
The LPC2131/2132/2138 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2138 UART1 provides a full modem control handshake interface, too.
6.13.1 Features
* * * * * *
16 byte Receive and Transmit FIFOs. Register locations conform to `550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes Built-in baud rate generator. Standard modem interface signals included on UART1. (LPC2138 only) The LPC2131/2132/2138 transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs and hardware (CTS/RTS) flow control on the LPC2138 UART1 only.
6.14 I2C-bus serial I/O controller
The LPC2131/2132/2138 each contain two I2C-bus controllers. The I2C-bus is bi-directional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2131/2132/2138 supports bit rates up to 400 kbit/s (Fast I2C).
6.14.1 Features
* * * * * *
Standard I2C compliant bus interface. Easy to configure as Master, Slave, or Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus.
* Serial clock synchronization allows devices with different bit rates to communicate via * Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
* The I2C-bus may be used for test and diagnostic purposes.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
18 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.15 SPI serial I/O controller
The LPC2131/2132/2138 each contain one SPI controller. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
6.15.1 Features
* * * *
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined SPI master and slave. Maximum data bit rate of one eighth of the input clock rate.
6.16 SSP serial I/O controller
The LPC2131/2132/2138 each contain one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSITM, or MicrowireTM bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data.
6.16.1 Features
* Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire
buses.
* * * *
Synchronous Serial Communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. Four bits to 16 bits per frame.
6.17 General purpose timers/counters
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock, and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with `or' and `and', as well as `broadcast' functions among them.
6.17.1 Features
* A 32-bit Timer/Counter with a programmable 32-bit Prescaler. * Counter or timer operation. * Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an interrupt.
9397 750 14008 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
19 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
* Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Four external outputs per timer corresponding to match registers, with the following
capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
6.18 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to `feed' (or reload) the watchdog within a predetermined amount of time.
6.18.1 Features
* Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
* * * *
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (TPCLK x 256 x 4) to (TPCLK x 232 x 4) in multiples of TPCLK x 4.
6.19 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
6.19.1 Features
* Measures the passage of time to maintain a calendar and clock. * Ultra-low power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
* Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the
external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider allows fine adjustment of the RTC.
9397 750 14008 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
20 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
* Dedicated power supply pin can be connected to a battery or the main 3.3 V. 6.20 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2131/2132/2138. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).
6.20.1 Features
* Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
* The match registers also allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
* Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
* Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
9397 750 14008 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
21 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
* Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must `release' new match values before they can become effective.
* May be used as a standard timer if the PWM mode is not enabled. * A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 6.21 System control
6.21.1 Crystal oscillator
The oscillator supports crystals in the range of 10 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.21.2 "PLL" for additional information.
6.21.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s.
6.21.3 Reset and wake-up timer
Reset has two sources on the LPC2131/2132/2138: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip Flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a
9397 750 14008 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
22 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
6.21.4 Brown-out detector
The LPC2131/2132/2138 include 2-stage monitoring of the voltage on the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. The second stage of low-voltage detection asserts reset to inactivate the LPC2131/2132/2138 when the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of the Flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the POR circuitry maintains the overall reset. Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition.
6.21.5 Code security
This feature of the LPC2131/2132/2138 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip boot-loader detects a valid checksum in Flash and reads 0x87654321 from address 0x1FC in Flash, debugging will be disabled and thus the code in Flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase.
6.21.6 External interrupt inputs
The LPC2131/2132/2138 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.
6.21.7 Memory Mapping Control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip Flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
6.21.8 Power Control
The LPC2131/2132/2138 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
23 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
6.21.9 VPB bus
The VPB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first is to provide peripherals with the desired PCLK via VPB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be slowed down to 12 to 14 of the processor clock rate. Because the VPB bus must work properly at power-up (and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at 14 of the processor clock rate. The second purpose of the VPB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the VPB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
6.22 Emulation and debugging
The LPC2131/2132/2138 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself.
6.22.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
24 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.22.2 Embedded trace
Since the LPC2131/2132/2138 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace MacrocellTM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.
6.22.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2131/2132/2138 contain a specific configuration of RealMonitor software programmed into the on-chip Flash memory.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
25 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
7. Limiting values
Table 9: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Symbol VDD VDDA VBAT VREF VIA VI VI IDD ISS Tstg Ptot Parameter supply voltage, core and external rail analog 3.3 V pad supply voltage RTC power supply voltage A/D converter reference voltage analog input voltage on A/D related pins DC input voltage, 5 V tolerant I/O pins DC input voltage, other I/O pins DC supply current per supply pin DC ground current per ground pin storage temperature [6] total power dissipation (based on package heat transfer, not device power consumption)
[2] [3] [2]
Conditions
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -40 -
Max +3.6 4.6 4.6 4.6 5.1 6.0 VDD + 0.5 [4] 100 [5] 100 [5] 125 1.5
Unit V V V V V V V mA mA C W
[1]
The following applies to the Limiting values: a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Section 8 "Static characteristics"and Section 9 "Dynamic characteristics" of this specification is not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Including voltage on outputs in 3-state mode. Only valid when the VDD supply voltage is present. Not to exceed 4.6 V. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type.
[2] [3] [4] [5] [6]
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
26 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
8. Static characteristics
Table 10: DC characteristics Ta = -40 C to +85 C for commercial, unless otherwise specified. Symbol Parameter VDD VDDA VBAT VREF supply voltage, core and external rail analog 3.3 V pad supply voltage RTC supply voltage A/D converter reference voltage LOW-level input current HIGH-level input current 3-state output leakage current I/O latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output LOW-level output voltage [5] IOH = -4 mA IOL = -4 mA VOL = 0.4 V VOH = 0 VOL = VDDA VI = 5 V [7] VI = 0 VDD < VI < 5 V [7] VDD = 3.3 V, CCLK = 60 MHz, Ta = 25 C, code voltage [5] output active VI = 0 V; no pull-up VI = VDD; no-pull-down VO = 0 V, VO = VDD; no pull-up/down -(0.5 VDD) < V < (1.5 VDD) Tj < 125 C VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu IDD
[2] [3] [4]
Conditions
Min 3.0 2.5 3.0 3.0
Typ [1] 3.3 3.3 3.3 3.3
Max 3.6 3.6 3.6 3.6
Unit V V V V
Standard port pins, RESET, RTCK IIL IIH IOZ Ilatch 0 0 2.0 VDD - 0.4 -4 4 10 -15 0 0.4 50 -50 0 3 3 3 100 5.5 VDD 0.8 0.4 -45 50 150 -85 0 A A A mA V V V V V V V mA mA mA mA A A A mA
HIGH-level output current [5] VOH = VDD - 0.4 V LOW-level output current [5] HIGH-level short circuit current [6] LOW-level short circuit current [6] pull-down current pull-up current (applies to P1.16 to P1.25) active mode supply current
while(1){}
executed from FLASH, no active peripherals Power-down mode I2C-bus VIH VIL
9397 750 14008
VDD = 3.3 V, Ta = +25 C, VDD = 3.3 V, Ta = +85 C
0.7Vtol -
-
0.3Vtol
A A V V
27 of 36
pins HIGH-level input voltage LOW-level input voltage Vtol is from 4.5 V to 5.5 V Vtol is from 4.5 V to 5.5 V
Rev. 01 -- 18 November 2004
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table 10: DC characteristics ...continued Ta = -40 C to +85 C for commercial, unless otherwise specified. Symbol Parameter Vhys VOL ILI hysteresis voltage LOW-level output voltage [5] Conditions Vtol is from 4.5 V to 5.5 V IOLS = 3 mA VI = 5 V Oscillator pins VXTAL1 VXTAL2 VRTXC1 VRTXC2
[1] [2] [3] [4] [5] [6] [7]
Min 0 0 0 0
Typ [1] 0.5Vtol 2 10 -
Max 0.4 4 22 1.8 1.8 1.8 1.8
Unit V V A A V V V V
input leakage current to VSS VI = VDD
XTAL1 input voltages XTAL2 output voltages RTXC1 input voltages RTXC2 output voltages
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. Including voltage on outputs in 3-state mode. VDD supply voltages must be present. 3-state outputs go into 3-state mode when VDD is grounded. Accounts for 100 mV voltage drop in all supply lines. Only allowed for a short time period. Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
Table 11: A/D converter DC electrical characteristics VDDA = 2.5 V to 3.6 V unless otherwise specified; Ta = -40 C to +85 C unless otherwise specified; A/D converter frequency 4.5 MHz. Symbol VIA Ciss ED EL(adj) EO EG ET
[1] [2] [3] [4] [5] [6] [7]
Parameter analog input voltage analog input capacitance differential non-linearity integral non-linearity offset error gain error absolute error
Conditions
Min 0 [1] [2] [3] [1] [4] [1] [5] [1] [6] [1] [7]
Typ -
Max VDDA 1 1 2 3 0.5 4
Unit V pF LSB LSB LSB % LSB
-
Conditions: VSSA = 0 V, VDDA = 3.3 V. The A/D is monotonic, there are no missing codes. The differential non-linearity (ED) is the difference between the actual step width and the ideal step width. See Figure 4. The integral no-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 4. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 4. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 4. The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated A/D and the ideal transfer curve. See Figure 4.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
28 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
offset error EO 1023
gain error EG
1022
1021
1020
1019
1018
(2)
7 code out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024
0 1 2 3 4 5 6 7 VIA (LSBideal) offset error EO
1 LSB =
VDDA - VSSA 1024
002aab136
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 4. A/D conversion characteristics.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
29 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
9. Dynamic characteristics
Table 12: AC characteristics Ta = 0 C to +70 C for commercial, -40 C to +85 C for industrial, VDD over specified ranges [1] Symbol External clock fosc Tclk tCHCX tCLCX tCLCH tCHCL tr(O) tf(O) tof oscillator frequency oscillator clock period clock HIGH time clock LOW time clock rise time clock fall time output rise time output fall time output fall time VIH to VIL 10 40 Tclk x 0.4 Tclk x 0.4 20 + 0.1 x Cb [2] 10 10 25 100 5 5 MHz ns ns ns ns ns ns ns ns Parameter Conditions Min Typ [1] Max Unit
Port pins (except P0.2 and P0.3)
I2C-bus pins (P0.2 and P0.3)
[1] [2]
Parameters are valid over operating temperature range unless otherwise specified. Bus capacitance Cb in pF, from 10 pF to 400 pF.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
30 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
9.1 Timing
VDD - 0.5 V 0.45 V
0.2VDD + 0.9 0.2VDD - 0.1 V tCHCX tCHCL tCLCX Tclk tCLCH
002aab137
Fig 5. External clock timing.
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
31 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
10. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 6. Package outline SOT314-2 (LQFP64).
9397 750 14008 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
32 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
11. Abbreviations
Table 13: Acronym ADC BOD CPU DAC DCC FIFO GPIO PLL POR PWM RAM SRAM UART VIC VPB Acronym list Description Analog-to-Digital Converter Brown-Out Detection Central Processing Unit Digital-to-Analog Converter Debug Communications Channel First In, First Out General Purpose Input/Output Phase-Locked Loop Power-On Reset Pulse Width Modulator Random Access Memory Static Random Access Memory Universal Asynchronous Receiver/Transmitter Vector Interrupt Controller VLSI Peripheral Bus
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
33 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
12. Revision history
Table 14: Revision history Release date Data sheet status Change notice Doc. number Supersedes Preliminary data sheet 9397 750 14008 Document ID
LPC2131_2132_2138 20041118 _1
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
34 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
13. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
14. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
16. Licenses
Purchase of Philips I2C-bus components Purchase of Philips I2C-bus components conveys a license under the Philips' I2C-bus patent to use the components in the I2C-bus system provided the system conforms to the I2C-bus specification defined by Koninklijke Philips Electronics N.V. This specification can be ordered using the code 9398 393 40011.
15. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process
17. Trademarks
ARM -- is a registered trademark of ARM, Inc. ARM7TDMI-S -- is a trademark of ARM, Inc. EmbeddedICE -- is a registered trademark of ARM, Inc. Embedded Trace Macrocell -- is a trademark of ARM, Inc. Microwire -- is a trademark of National Semiconductors, Inc. RealMonitor -- is a trademark of ARM, Inc. SPI -- is a trademark of Motorola, Inc. SSI -- is a trademark of Texas Instruments, Inc. Thumb -- is a registered trademark of ARM, Inc.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14008
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 01 -- 18 November 2004
35 of 36
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
19. Contents
1 2 2.1 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 7 8 9 9.1 10 11 12 13 14 15 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 9 Architectural overview. . . . . . . . . . . . . . . . . . . . 9 On-Chip Flash program memory . . . . . . . . . . . 9 On-Chip static RAM . . . . . . . . . . . . . . . . . . . . . 9 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 10 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 12 Pin function select register 0 (PINSEL0 0xE002C000) . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin function select register 1 (PINSEL1 0xE002C004) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin function select register 2 (PINSEL2 0xE002C014) . . . . . . . . . . . . . . . . . . . . . . . . . 16 General purpose parallel I/O. . . . . . . . . . . . . . 17 10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 17 10-bit D/A converter . . . . . . . . . . . . . . . . . . . . 17 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C-bus serial I/O controller . . . . . . . . . . . . . . 18 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 19 SSP serial I/O controller . . . . . . . . . . . . . . . . . 19 General purpose timers/counters . . . . . . . . . . 19 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 20 Pulse width modulator . . . . . . . . . . . . . . . . . . 21 System control . . . . . . . . . . . . . . . . . . . . . . . . 22 Emulation and debugging . . . . . . . . . . . . . . . . 24 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Static characteristics. . . . . . . . . . . . . . . . . . . . 27 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 34 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 35 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16 17 18 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Contact information . . . . . . . . . . . . . . . . . . . . 35
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 November 2004 Document number: 9397 750 14008
Published in the U.S.A.

▲Up To Search▲

Price & Availability of LPC2132

	To Download LPC2132 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .